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Title:A configurable mixed-precision convolution processing unit generator in Chisel
Authors:ID Vreča, Jure, Institut Jožef Stefan (Author)
ID Biasizzo, Anton, Institut Jožef Stefan (Author)
Files:URL URL - Source URL, visit https://ieeexplore.ieee.org/document/10139758
 
.pdf PDF - Presentation file, download (332,90 KB)
MD5: 1D9BB8C9121F802E7E4CEA0F59DCFA95
 
Language:English
Typology:1.08 - Published Scientific Conference Contribution
Organization:Logo IJS - Jožef Stefan Institute
Keywords:neural networks, quantization, Chisel, FPGA
Publication status:Published
Publication version:Submitted Version
Publication date:02.06.2023
Publisher:IEEE
Year of publishing:2023
Number of pages:Str. [1-4]
Source:ZDA
PID:20.500.12556/DiRROS-16621 New window
UDC:004
ISSN on article:2473-2117
DOI:10.1109/DDECS57882.2023.10139758 New window
COBISS.SI-ID:154805763 New window
Copyright:© 2023 IEEE
Note:Nasl. z nasl. zaslona; Opis vira z dne 7. 6. 2023;
Publication date in DiRROS:08.06.2023
Views:723
Downloads:472
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Record is a part of a journal

Title:IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems
Shortened title:IEEE Int. Symp. Des. Diagn. Electron. Circuits Syst.
Publisher:Institute of Electrical and Electronics Engineers, Inc.
ISSN:2473-2117
COBISS.SI-ID:154802435 New window

Document is financed by a project

Funder:ARRS - Slovenian Research Agency
Project number:P2-0098
Name:Računalniške strukture in sistemi

Funder:EC - European Commission
Funding programme:H2020
Project number:101007273
Name:Distributed Artificial Intelligent Systems
Acronym:DAIS

Secondary language

Language:Slovenian
Keywords:nevronske mreže, Chisel, FPGA


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