20.500.12556/DiRROS-16621 A configurable mixed-precision convolution processing unit generator in Chisel neural networks quantization Chisel FPGA nevronske mreže Chisel FPGA true false false IEEE ZDA Angleški jezik Slovenski jezik © 2023 IEEE Neznano 2023-06-08 14:29:12 2023-06-08 14:29:13 2023-06-10 03:43:30 0000-00-00 00:00:00 2023 0 0 Nasl. z nasl. zaslona; Opis vira z dne 7. 6. 2023; Str. [1-4] 0000-00-00 PreprintVObjavi Objavljeno NiDoloceno 0000-00-00 0000-00-00 2023-06-02 004 2473-2117 10.1109/DDECS57882.2023.10139758 154805763 https://ieeexplore.ieee.org/document/10139758 1 5034822b-05e7-11ee-9634-001a4af901a5 https://dirros.openscience.si/Dokument.php?lang=slv&id=22517 RAZ_Vreca_Jure_2023.pdf RAZ_Vreca_Jure_2023.pdf 1 1D9BB8C9121F802E7E4CEA0F59DCFA95 d64a85c04ecf64e1149bf89b687f8d34723f4da7dffe851c15537df22bd0e561 d280ab94-05ea-11ee-9634-001a4af901a5 https://dirros.openscience.si/Dokument.php?lang=slv&id=22521 Institut Jožef Stefan 0 0 0