Title: | A configurable mixed-precision convolution processing unit generator in Chisel |
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Authors: | ID Vreča, Jure, Institut Jožef Stefan (Author) ID Biasizzo, Anton, Institut Jožef Stefan (Author) |
Files: | URL - Source URL, visit https://ieeexplore.ieee.org/document/10139758
PDF - Presentation file, download (332,90 KB) MD5: 1D9BB8C9121F802E7E4CEA0F59DCFA95
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Language: | English |
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Typology: | 1.08 - Published Scientific Conference Contribution |
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Organization: | IJS - Jožef Stefan Institute
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Keywords: | neural networks, quantization, Chisel, FPGA |
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Publication status: | Published |
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Publication version: | Submitted Version |
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Publication date: | 02.06.2023 |
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Publisher: | IEEE |
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Year of publishing: | 2023 |
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Number of pages: | Str. [1-4] |
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Source: | ZDA |
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PID: | 20.500.12556/DiRROS-16621 ![Link is opened in a new window New window](teme/dirros/img/NovoOkno.png) |
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UDC: | 004 |
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ISSN on article: | 2473-2117 |
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DOI: | 10.1109/DDECS57882.2023.10139758 ![Link is opened in a new window New window](teme/dirros/img/NovoOkno.png) |
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COBISS.SI-ID: | 154805763 ![Link is opened in a new window New window](teme/dirros/img/NovoOkno.png) |
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Copyright: | © 2023 IEEE |
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Note: | Nasl. z nasl. zaslona;
Opis vira z dne 7. 6. 2023;
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Publication date in DiRROS: | 08.06.2023 |
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Views: | 509 |
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Downloads: | 325 |
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Metadata: | ![Export as DC-RDF DC-RDF](teme/dirros/img/icon_dc_rdf.gif) |
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