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Title: Design and analysis of low power rapid charge holding dynamic latched comparator Authors: ID Thirunavukkarasu, Jaspar Vinitha Sundari (Author) ID Kuppusamy, Paramasivam (Author) Files: PDF - Presentation file, download (3,08 MB) MD5: 7E35D877646C614A3FACE1D1712E85BF   URL - Source URL, visit https://ojs.midem-drustvo.si/index.php/InfMIDEM/article/view/2113   URL - Source URL, visit https://ojs.midem-drustvo.si/index.php/InfMIDEM/article/view/2113   This document has even more files. Complete list of files is available below. Language: English Typology: 1.01 - Original Scientific Article Organization: MIDEM - Society for Microelectronics, Electronic Components and Materials Abstract: The need for portable devices with high precision has raised the demand for optimization of power and delay in various dynamic comparator topologies. In this paper, an efficient architecture that does timely yet rapid comparison with reduced power dissipation and optimal energy per comparison is proposed. Introducing an extra tail transistor in preamplifier of comparator, assists in holding the high gain, thereby reducing delay as well as power. The latch is meanwhile ready with a minimum threshold value at its output nodes with the help of a pass transistor in between latch output nodes. The conventional, hybrid, and proposed architecture, namely Low power Rapid Charge Holding Dynamic Latched Comparator (LRCHDLC) are simulated and verified for power, delay, and energy efficiency in Cadence Virtuoso Spectre. The proposed technique shows a significant improvement in delay and power consumption when compared to conventional comparators. Monte Carlo simulation shows that the proposed technique is robust to the process mismatch, sustaining optimal power, delay and energy efficiency. Keywords: average power consumption, latch regeneration delay, hybrid dynamic latched comparator, rapid charge holding latched comparator Publication status: Published Publication version: Version of Record Publication date: 01.01.2025 Year of publishing: 2025 Number of pages: str. 201-217 Numbering: Vol. 55, no. 4 PID: 20.500.12556/DiRROS-30242  UDC: 621.38:621.375.4 ISSN on article: 0352-9045 DOI: 10.33180/InfMIDEM2025.401  COBISS.SI-ID: 281578755  Note: Besedilo v angl.; Publication date in DiRROS: 18.06.2026 Views: 125 Downloads: 132 Metadata:    Cite this work Plain text BibTeX EndNote XML EndNote/Refer RIS ABNT ACM Ref AMA APA Chicago 17th Author-Date Harvard IEEE ISO 690 MLA Vancouver : Copy citation

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Title:	Informacije MIDEM : časopis za mikroelektroniko, elektronske sestavne dele in materiale
Shortened title:	Inf. MIDEM
Publisher:	Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale
ISSN:	0352-9045
COBISS.SI-ID:	1220612

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License:	CC BY 4.0, Creative Commons Attribution 4.0 International
Link:	http://creativecommons.org/licenses/by/4.0/
Description:	This is the standard Creative Commons license that gives others maximum freedom to do what they want with the work as long as they credit the author.

Secondary language

Language:	Slovenian
Title:	Oblikovanje in analiza dinamičnega komparatorja z zapahom z nizko porabo energije in hitrim polnjenjem
Abstract:	Potreba po prenosnih napravah z visoko natančnostjo je povečala povpraševanje po optimizaciji moči in zamika v različnih dinamičnih topologijah komparatorjev. V članku je predlagana učinkovita arhitektura, ki omogoča pravočasno in hkrati hitro primerjavo z zmanjšano porabo energije. Dodajanje dodatnega repnega tranzistorja v predojačevalnik komparatorja pomaga ohraniti visoko ojačenje, s čimer se zmanjša zakasnitev in poraba energije. Zapah je medtem pripravljen z minimalno mejno vrednostjo na izhodnih vozliščih. Konvencionalna, hibridna in predlagana arhitektura, imenovana Low power Rapid Charge Holding Dynamic Latched Comparator (LRCHDLC), je simulirana in preverjena glede moči, zakasnitve in energetske učinkovitosti v Cadence Virtuoso Spectre. Predlagana tehnika kaže znatno izboljšanje zakasnitve in porabe moči v primerjavi s konvencionalnimi komparatorji. Simulacija Monte Carlo kaže, da je predlagana tehnika odporna na neskladje procesov, pri čemer ohranja optimalno moč, zakasnitev in energetsko učinkovitost.
Keywords:	povprečna poraba energije, zakasnitev regeneracije zapaha, hibridni dinamični komparator z zapahom, hitro polnjenje

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