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Title:Towards deploying highly quantized neural networks on FPGA using chisel
Authors:ID Vreča, Jure, Institut Jožef Stefan (Author)
ID Biasizzo, Anton, Institut Jožef Stefan (Author)
Files:URL URL - Source URL, visit https://ieeexplore.ieee.org/document/10456782/authors#authors
 
.pdf PDF - Presentation file, download (419,83 KB)
MD5: C6531548B85A232A34C012D82828C084
 
Language:English
Typology:1.08 - Published Scientific Conference Contribution
Organization:Logo IJS - Jožef Stefan Institute
Abstract:We present chisel4ml, a Chisel-based tool that generates hardware for highly quantized neural networks described in QKeras. Such networks typically use parameters with bitwidths less than 8 bits and may have pruned connections. Chisel4ml can generate the highly quantized neural network as a single combinational circuit with pipeline registers in between the different layers. It supports heterogeneous quantization where each layer can have a different precision. The full parallelization enables very low-latency and high throughput inference, that are required for certain tasks. We illustrate this on the triggering system for the CERN Large Hadron Collider, which filters out events of interest and sends them on for further processing. We compare our tool against hls4ml, a high-level synthesis based approach for deploying similar neural networks. Chisel4ml is still under development. However, it already achieves comparable results to hls4ml for some neural network architectures. Chisel4ml is available on https://github.com/cs-jsi/chisel4ml.
Keywords:neural networks, QKeras, Chisel4ml
Publication status:Published
Publication version:Author Accepted Manuscript
Publication date:19.03.2023
Publisher:IEEE
Year of publishing:2023
Number of pages:Str. 161-167
Source:ZDA
PID:20.500.12556/DiRROS-18802 New window
UDC:004
DOI:10.1109/DSD60849.2023.00032 New window
COBISS.SI-ID:190218499 New window
Copyright:©2023 IEEE
Note:Nasl. z nasl. zaslona; Opis vira z dne 25. 3. 2024;
Publication date in DiRROS:23.04.2024
Views:389
Downloads:246
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Record is a part of a monograph

Title:2023 26th Euromicro Conference on Digital System Design : DSD 2023
Place of publishing:Los Alamitos (CA)
Publisher:IEEE
ISBN:979-8-3503-4419-6
COBISS.SI-ID:190215427 New window

Document is financed by a project

Funder:ARIS - Slovenian Research and Innovation Agency
Project number:P2-0098
Name:Računalniške strukture in sistemi

Funder:EC - European Commission
Funding programme:H2020
Project number:101007273
Name:Distributed Artificial Intelligent Systems
Acronym:DAIS

Funder:EC - European Commission
Funding programme:H2020
Project number:876038
Name:Intelligent Secure Trustable Things
Acronym:InSecTT

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