1. Towards deploying highly quantized neural networks on FPGA using chiselJure Vreča, Anton Biasizzo, 2023, published scientific conference contribution Abstract: We present chisel4ml, a Chisel-based tool that generates hardware for highly quantized neural networks described in QKeras. Such networks typically use parameters with bitwidths less than 8 bits and may have pruned connections. Chisel4ml can generate the highly quantized neural network as a single combinational circuit with pipeline registers in between the different layers. It supports heterogeneous quantization where each layer can have a different precision. The full parallelization enables very low-latency and high throughput inference, that are required for certain tasks. We illustrate this on the triggering system for the CERN Large Hadron Collider, which filters out events of interest and sends them on for further processing. We compare our tool against hls4ml, a high-level synthesis based approach for deploying similar neural networks. Chisel4ml is still under development. However, it already achieves comparable results to hls4ml for some neural network architectures. Chisel4ml is available on https://github.com/cs-jsi/chisel4ml.
Keywords: neural networks, QKeras, Chisel4ml
Published in DiRROS: 23.04.2024; Views: 53; Downloads: 30
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2. Hardware–software co-design of an audio feature extraction pipeline for machine learning applicationsJure Vreča, Ratko Pilipović, Anton Biasizzo, 2024, original scientific article Abstract: Keyword spotting is an important part of modern speech recognition pipelines. Typical contemporary keyword-spotting systems are based on Mel-Frequency Cepstral Coefficient (MFCC) audio features, which are relatively complex to compute. Considering the always-on nature of many keyword-spotting systems, it is prudent to optimize this part of the detection pipeline. We explore the simplifications of the MFCC audio features and derive a simplified version that can be more easily used in embedded applications. Additionally, we implement a hardware generator that generates an appropriate hardware pipeline for the simplified audio feature extraction. Using Chisel4ml framework, we integrate hardware generators into Python-based Keras framework, which facilitates the training process of the machine learning models using our simplified audio features.
Keywords: FPGA, MFCC, keyword spotting, chisel
Published in DiRROS: 25.03.2024; Views: 112; Downloads: 52
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