Povzetek: This paper presents the design and optimization of a parametric multiple-channel Double Dynamic Switching Biased Complementary Folded-Cascode Amplifier with switched capacitor integrator application in 32nm FinFET technology. The LTspice simulations demonstrate that the amplifier can attain an open-loop DC gain of 44.8dB, and a phase margin of about 87.8° with ±0.5V supply voltages. Moreover, the amplifier power consumption is measured 246µW including bias circuitry and a Gain-Bandwidth Product (GBW) of 77.45MHz under a 5pF load capacitor. The circuit’s stability enables it to offer diverse design capabilities tailored to specific application needs. This novel design is capable of reducing supply voltages and power dissipationKljučne besede: 32nm finfet technology, complementary folded-cascode amplifier, double dynamic switching bias, self-cascode, switched capacitorObjavljeno v DiRROS: 18.06.2026; Ogledov: 244; Prenosov: 255 Celotno besedilo (1,68 MB)Gradivo ima več datotek! Več...
