20.500.12556/DiRROS-30242 Design and analysis of low power rapid charge holding dynamic latched comparator Oblikovanje in analiza dinamičnega komparatorja z zapahom z nizko porabo energije in hitrim polnjenjem The need for portable devices with high precision has raised the demand for optimization of power and delay in various dynamic comparator topologies. In this paper, an efficient architecture that does timely yet rapid comparison with reduced power dissipation and optimal energy per comparison is proposed. Introducing an extra tail transistor in preamplifier of comparator, assists in holding the high gain, thereby reducing delay as well as power. The latch is meanwhile ready with a minimum threshold value at its output nodes with the help of a pass transistor in between latch output nodes. The conventional, hybrid, and proposed architecture, namely Low power Rapid Charge Holding Dynamic Latched Comparator (LRCHDLC) are simulated and verified for power, delay, and energy efficiency in Cadence Virtuoso Spectre. The proposed technique shows a significant improvement in delay and power consumption when compared to conventional comparators. Monte Carlo simulation shows that the proposed technique is robust to the process mismatch, sustaining optimal power, delay and energy efficiency. Potreba po prenosnih napravah z visoko natančnostjo je povečala povpraševanje po optimizaciji moči in zamika v različnih dinamičnih topologijah komparatorjev. V članku je predlagana učinkovita arhitektura, ki omogoča pravočasno in hkrati hitro primerjavo z zmanjšano porabo energije. Dodajanje dodatnega repnega tranzistorja v predojačevalnik komparatorja pomaga ohraniti visoko ojačenje, s čimer se zmanjša zakasnitev in poraba energije. Zapah je medtem pripravljen z minimalno mejno vrednostjo na izhodnih vozliščih. Konvencionalna, hibridna in predlagana arhitektura, imenovana Low power Rapid Charge Holding Dynamic Latched Comparator (LRCHDLC), je simulirana in preverjena glede moči, zakasnitve in energetske učinkovitosti v Cadence Virtuoso Spectre. Predlagana tehnika kaže znatno izboljšanje zakasnitve in porabe moči v primerjavi s konvencionalnimi komparatorji. Simulacija Monte Carlo kaže, da je predlagana tehnika odporna na neskladje procesov, pri čemer ohranja optimalno moč, zakasnitev in energetsko učinkovitost. average power consumption latch regeneration delay hybrid dynamic latched comparator rapid charge holding latched comparator povprečna poraba energije zakasnitev regeneracije zapaha hibridni dinamični komparator z zapahom hitro polnjenje true false true Angleški jezik Slovenski jezik Neznano 2026-06-17 19:14:59 2026-06-18 05:59:31 2026-07-02 03:59:36 0000-00-00 00:00:00 2025 0 0 Besedilo v angl.; str. 201-217 no. 4 Vol. 55 2025 0000-00-00 Zaloznikova Objavljeno NiDoloceno 0000-00-00 0000-00-00 2025-01-01 621.38:621.375.4 0352-9045 10.33180/InfMIDEM2025.401 281578755 MIDEM_55(2025)4p1.pdf MIDEM_55(2025)4p1.pdf 1 7E35D877646C614A3FACE1D1712E85BF bef9cd2cce5ff2501fe9d90e889fd5fea9b8a616a6fb5375677493ee408c1997 73992006-7528-11f1-b0d9-001a4af901a5 https://dirros.openscience.si/Dokument.php?lang=slv&id=46808 https://ojs.midem-drustvo.si/index.php/InfMIDEM/article/view/2113 1 1287da86-6a70-11f1-97b2-001a4af901a5 https://dirros.openscience.si/Dokument.php?lang=slv&id=45812 \"https://www.midem-drustvo.si/journal_papers/MIDEM_55(2025)4p1.pdf 1 6a3835db-7528-11f1-b0d9-001a4af901a5 https://dirros.openscience.si/Dokument.php?lang=slv&id=46785 https://ojs.midem-drustvo.si/index.php/InfMIDEM/article/view/2113 1 1cc88f5d-6aca-11f1-a3b9-001a4af901a5 https://dirros.openscience.si/Dokument.php?lang=slv&id=45833 RAZ_Thirunavukkarasu_Jaspar_Vinitha_Sundari_2025.pdf RAZ_Thirunavukkarasu_Jaspar_Vinitha_Sundari_2025.pdf 1 25EC64CBF35E35745352C2E4AFA409AE e66b74469140f7bf68156b7ebfe687a0eba0b7d5215dde2de66bafd6671cf79a 2105a25b-7386-11f1-a785-001a4af901a5 https://dirros.openscience.si/Dokument.php?lang=slv&id=46412 Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale Informacije MIDEM 0 0 0