Design and optimization of multiple-channel double dynamic switching biased Op-Amp for switched capacitor integrator using FinFET technologyBabaeian Far, Morteza (Avtor) Ormanci, Mehmet Aytuğ (Avtor) Kaçar, Firat (Avtor) 32nm finfet technologycomplementary folded-cascode amplifierdouble dynamic switching biasself-cascodeswitched capacitorThis paper presents the design and optimization of a parametric multiple-channel Double Dynamic Switching Biased Complementary Folded-Cascode Amplifier with switched capacitor integrator application in 32nm FinFET technology. The LTspice simulations demonstrate that the amplifier can attain an open-loop DC gain of 44.8dB, and a phase margin of about 87.8° with ±0.5V supply voltages. Moreover, the amplifier power consumption is measured 246µW including bias circuitry and a Gain-Bandwidth Product (GBW) of 77.45MHz under a 5pF load capacitor. The circuit’s stability enables it to offer diverse design capabilities tailored to specific application needs. This novel design is capable of reducing supply voltages and power dissipation20252026-06-17 19:09:15Neznano30227UDK: 621.375ISSN pri članku: 0352-9045DOI: 10.33180/InfMIDEM2025.105COBISS_ID: 281427203sl