<?xml version="1.0"?>
<metadata xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:dc="http://purl.org/dc/elements/1.1/"><dc:title>A configurable mixed-precision convolution processing unit generator in Chisel</dc:title><dc:creator>Vreča,	Jure	(Avtor)
	</dc:creator><dc:creator>Biasizzo,	Anton	(Avtor)
	</dc:creator><dc:subject>neural networks</dc:subject><dc:subject>quantization</dc:subject><dc:subject>Chisel</dc:subject><dc:subject>FPGA</dc:subject><dc:publisher>IEEE </dc:publisher><dc:date>2023</dc:date><dc:date>2023-06-08 14:29:12</dc:date><dc:type>Neznano</dc:type><dc:identifier>16621</dc:identifier><dc:identifier>UDK: 004</dc:identifier><dc:identifier>ISSN pri članku: 2473-2117</dc:identifier><dc:identifier>DOI: 10.1109/DDECS57882.2023.10139758</dc:identifier><dc:identifier>COBISS_ID: 154805763</dc:identifier><dc:source>ZDA</dc:source><dc:language>sl</dc:language><dc:rights>© 2023 IEEE</dc:rights></metadata>
