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<rdf:RDF xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:dc="http://purl.org/dc/elements/1.1/"><rdf:Description rdf:about="https://dirros.openscience.si/IzpisGradiva.php?id=16621"><dc:title>A configurable mixed-precision convolution processing unit generator in Chisel</dc:title><dc:creator>Vreča,	Jure	(Avtor)
	</dc:creator><dc:creator>Biasizzo,	Anton	(Avtor)
	</dc:creator><dc:subject>neural networks</dc:subject><dc:subject>quantization</dc:subject><dc:subject>Chisel</dc:subject><dc:subject>FPGA</dc:subject><dc:publisher>IEEE </dc:publisher><dc:date>2023</dc:date><dc:date>2023-06-08 14:29:12</dc:date><dc:type>Neznano</dc:type><dc:identifier>16621</dc:identifier><dc:source>ZDA</dc:source><dc:language>sl</dc:language><dc:rights>© 2023 IEEE</dc:rights></rdf:Description></rdf:RDF>